1. Field of the Invention
The present invention relates to a circuit carrier and a semiconductor package using the same, more particularly, to a circuit carrier forming a brown-oxide layer on a bonding pad of a substrate and a semiconductor package using the same.
2. Description of Related Art
The flip chip interconnect technology for connecting a die to a carrier can be summarized as follows. A plurality of pads is arranged on an active surface of the die in area arrays, and bumps (i.e. solder bumps) are formed on the pads with the under bump metallurgy (UBM) therebetween. Then, the die is flipped. The pads on the active surface of the chip electrically and structurally connect to a plurality of contacts on the surface of a carrier (i.e. a substrate or a printed circuit board) via the bumps. It should be noted that the flip chip interconnect technology is suitable for high pin count chip packages and has the advantages of minimizing the package region and shortening the signal transmission path.
FIG. 1A is a schematic cross-sectional view illustrating a conventional circuit carrier before bonding to a bump on a corresponding die. FIG. 1B is a schematic cross-sectional view illustrating the conventional circuit carrier, which is shown in FIG. 1A, after bonding to the bump on the corresponding die. Referring to FIG. 1A, a circuit carrier 100 mainly includes a substrate 110, a plurality of bonding pads 120a, and a solder mask 130. The substrate 110 includes a plurality of conductive layers, a plurality of insulating layers, and a plurality of conductive vias (none shown in the figures). Each insulating layer is disposed between two adjacent conductive layers, and each conductive via passes through at least one insulating layer to be connected with at least two conductive layers. Moreover, the bonding pads 120a are disposed on a surface 112 of the substrate 110 for connecting a plurality of bumps 210 on a corresponding die 200 respectively. Here, the bumps 210 are flip chip solder bumps, for example. The bonding pads 120a can be constituted by a conductive circuit layer 120 on the outermost layer of the substrate 110. As the material of the conductive circuit layer 120 on the substrate 110 is usually copper, the material of the bonding pads 120a is also copper. A solder mask 130 covers on the surface 112 of the substrate 110 entirely, and the solder mask 130 has a plurality of openings 132 for exposing the bonding pads 120a individually.
As shown in FIG. 1B, when a reflow process is performed to connect the bumps 210 and the bonding pads 120a, the bumps 210 and the bonding pads 120a are well bonded. Consequently, the bumps 210 topple to enclose the bonding pads 120a entirely. Hence, the pitch between the circuit carrier 100 and the corresponding die 200 is reduced, thereby increasing the difficulty of the following process.
In addition, the openings 132 have the process tolerance during the manufacture of the solder mask 130, such that the shift may occur to the solder mask 130. As for the fine pitch elements, the aforesaid factors all elevate the difficulty in the manufacture of circuit carriers.